MM74HC137中文资料3-to-8 Line Decoder With Address Latches (Inverted Output)数据手册TI规格书

描述 Description

General Description
This device utilizes advanced silicon-gate CMOS technology, to implement a three-to-eight line decoder with latches on the three address inputs. When GLgoes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GLremains high no address changes will be recognized.

特性 Features

Typical propagation delay: 20 ns
Wide supply range: 2± 6V
Latched inputs for easy interfacing.
Fanout of 10 LS-TTL loads.