3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

3-to-8 Line Decoder With Address Latches (Inverted Output)

General Description\nThis device utilizes advanced silicon-gate CMOS technology, to implement a three-to-eight line decoder with latches on the three address inputs. When GLgoes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GLremains hig Typical propagation delay: 20 ns\nWide supply range: 2± 6V\nLatched inputs for easy interfacing.\nFanout of 10 LS-TTL loads.;

TI

德州仪器

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes 页数：6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司