Parallel-Load 8-Bit Shift Register

General Description The MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary output

文件：64.41 Kbytes 页数：6 Pages

Fairchild

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Parallel-Load 8-Bit Shift Register

General Description\nThe MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary outputs, ■ Wide supply voltage range: 3V to 15V\n■ Guaranteed noise margin: 1V\n■ High noise immunity: 0.45 VCC (typ.)\n■ Low power TTL compatibility: fan out of 2 driving 74L\n■ Parallel loading independent of clock\n■ Dual clock inputs\n■ Fully static operation;

ONSEMI

安森美半导体

Package：16-DIP（0.300"，7.62mm）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：并行或串行至串行 类别：集成电路（IC） 移位寄存器 描述：IC SHIFT REGISTER 8BIT 16DIP

ONSEMI

安森美半导体

Parallel-Load 8-Bit Shift Register

General Description The MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary output

文件：50.96 Kbytes 页数：6 Pages

Fairchild

仙童半导体