MM54HCT139J中文资料Dual 2-To-4 Line Decoder数据手册TI规格书

描述 Description

General Description
The MM54HCT139/MM74HCT139 is a high speed silicon gate CMOS decoder that is well suited to memory address decoding or data routing applications. It possesses an input threshold and output drive similar to LS-TTL and the low standby power of CMOS logic.
The device is comprised of two independent one-of-four decoders each with a single active low enable input (G1 or G2). Data on the select inputs (A1, B1 or A2, B2) cause one of the four normally high outputs to go low. All inputs to the decoder are protected from damage due to electrostatic discharge by diodes to VCC and ground. The
device is capable of driving 10 low power Schottky TTL equivalent loads.
The MM54HCT139/MM74HCT139 is functionally and pin equivalent to the 54LS139/74LS139 and can be used as a plug-in replacement to reduce system power consumption in existing systems.

特性 Features

■ Typical propagation delays: 20 ns
■ Low quiescent current: 40 mA maximum (74HCT Series)
■ Fanout of 10 LS-TTL loads