MM54HCT109J中文资料Dual J-K Flip-Flops with Preset and Clear数据手册TI规格书

描述 Description

General Description
These high speed J-K FLIP-FLOPS utilize advanced silicon gate CMOS technology. They possess the low power consumption and high noise immunity of standard CMOS inte grated circuits, along with the ability to drive 10 LS-TTL loads.
Each flip flop has independent J, K, PRESET, CLEAR, and CLOCK inputs and Q and Q outputs. These devices are edge sensitive to the clock input and change state on the positive going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input.
The 54HCT/74HCT logic family is functionally as well as pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static dis charge by internal diode clamps to VCC and ground.

特性 Features

■ Typical propagation delay: 20 ns
■ Low input current: 1 mA maximum
■ Low quiescent current: 40 mA maximum (74HCT Series)
■ Output drive capability: 10 LS-TTL loads