Dual J-K Flip-Flops with Preset and Clear

文件：123.94 Kbytes 页数：4 Pages

NSC

国半

Dual J-K Flip-Flops with Preset and Clear

TI

德州仪器

Dual J-K Flip-Flops with Preset and Clear

文件：123.94 Kbytes 页数：4 Pages

NSC

国半

Dual J-K Flip-Flops with Preset and Clear

General Description\nThese high speed J-K FLIP-FLOPS utilize advanced silicon gate CMOS technology. They possess the low power consumption and high noise immunity of standard CMOS inte grated circuits, along with the ability to drive 10 LS-TTL loads.\nEach flip flop has independent J, K, PRESET, CLE ■ Typical propagation delay: 20 ns\n■ Low input current: 1 mA maximum\n■ Low quiescent current: 40 mA maximum (74HCT Series)\n■ Output drive capability: 10 LS-TTL loads ;

TI

德州仪器