MK1707数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The MK1707 generates a low EMI output clock from a clock input. The part is designed to dither the LCD
interface clock for flat panel graphics controllers. The device uses ICS’ proprietary mix of analog and digital
Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the
frequency amplitude peaks by several dB.

特性 Features

• Packaged in 8-pin SOIC
• Available in Pb-free package
• Industrial temperature range available
• Provides a spread spectrum output clock
• Supports ATI’s flat panel controllers
• Guaranteed to +85°C operation
• Accepts a clock input, provides same frequency dithered output
• Good for all VGA modes from 80 to 167 MHz
• Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics
• Low EMI feature can be disabled
• Includes Power-down
• Operating voltage of 3.3 V or 5 V
• Advanced, low-power CMOS process