MCM69R736CZP4.4中文资料摩托罗拉数据手册PDF规格书

4M Late Write HSTL

The MCM69R736C/818C is a 4M–bit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R818C (organized as 256K words by 18 bits) and the MCM69R736C (organized as 128K words by 36 bits) are fabricated in Motorola’s high performance silicon gate BiCMOS technology.

The synchronous write and byte enables allow writing to individual bytes or the entire word.

The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.

• Byte Write Control

• Single 3.3 V +10, –5 Operation

• HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)

• HSTL — User Selectable Input Trip–Point

• HSTL — Compatible Programmable Impedance Output Drivers

• Register to Register Synchronous Operation

• Asynchronous Output Enable

• Boundary Scan (JTAG) IEEE 1149.1 Compatible

• Differential Clock Inputs

• Optional x18 or x36 Organization

• MCM69R736C/818C–4 = 4 ns

MCM69R736C/818C–4.4 = 4.4 ns

MCM69R736C/818C–5 = 5 ns

MCM69R736C/818C–6 = 6 ns

• Sleep Mode Operation (ZZ pin)

• 119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package