MCM63P736TQ100中文资料摩托罗拉数据手册PDF规格书

The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

• MCM63P736/MCM63P818–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

MCM63P736/MCM63P818–100 = 5 ns Access/10 ns Cycle (100 MHz)

MCM63P736/MCM63P818–66 = 7 ns Access/15 ns Cycle (66 MHz)

• 3.3 V + 10, – 5 Core Power Supply, 2.5 V or 3.3 V I/O Supply

• ADSP, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Two–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• Sleep Mode (ZZ)

• PB1 Version 2.0 Compatible

• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages