MCM63P631TQ4.5中文资料摩托罗拉数据手册PDF规格书

The MCM63P631 is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC, and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

• MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)

MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)

MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)

MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)

• Single 3.3 V + 10, – 5 Power Supply

• ADSP, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• Sleep Mode (ZZ)

• PB1 Version 2.0 Compatible

• Single–Cycle Deselect Timing

• JEDEC Standard 100–Pin TQFP Package