MC88916DWR2中文资料摩托罗拉数据手册PDF规格书

The MC88916 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems.

• Provides Performance Required to Drive 68030 Microprocessor Family as well as the 33 and 40MHz 68040 Microprocessors

• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input

• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’ Outputs Is Less Than 600ps (Derived From the TPD Specification, Which Defines the Part–to–Part Skew)

• SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4

• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency. Also a Q (180° Phase Shift) Output Available.

• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible

• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing