MC88915集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Low Skew CMOS PLL Clock Driver

The MC88915 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations.

Features

•Five Outputs (QO–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

•The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPDspecification, which defines the part–to–part skew)

•Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

•Input frequency range from 5MHz – 2X_Q FMAX spec

•Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q(180°phase shift) output available

•All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs.

All inputs are TTL–level compatible

•Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes