MC88915TFN55中文资料Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz Versions数据手册恩XP规格书

描述 Description

Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz VersionsThe MC88915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. For a 3.3V version, see the MC88LV915T data sheet.

特性 Features

• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part–to–part skew)
• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
• Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)
• Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q(180°phase shift) output available
• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL–level compatible. ±88mA IOL/IOHspecifications guarantee 50Ωtransmission line switching on the incident edge
• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3–state) for board test purposes
• Lock Indicator (LOCK) accuracy indicates a phase–locked state