LOW SKEW CMOS PLL CLOCK DRIVER

Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz Versions The MC88915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and

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Motorola

摩托罗拉

Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz Versions

Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz VersionsThe MC88915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and worksta • Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input\n• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part–to–part skew)\n• Input/Output ;

恩XP

恩智浦

IDT
SMD

IDT

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FREESCA
QFP64

FREESCA

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FREESCALE
QFP64

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

上传：深圳市振宏微科技有限公司