Octal Transparent Latch with 3?뭆tate Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

文件：117.48 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Octal Transparent Latch with 3?뭆tate Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

文件：117.48 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Octal Transparent Latch with 3-State Outputs

The MC74AC373/74ACT373 consists of eight latches with 3−state outputs for bus organized system applications. The flip−flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

文件：104.92 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Octal Transparent Latch with 3?뭆tate Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

文件：117.48 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Octal Transparent Latch with 3?뭆tate Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

文件：117.48 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

Octal Transparent Latch with 3-State Outputs

The MC74AC373/74ACT373 consists of eight latches with 3−state outputs for bus organized system applications. The flip−flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

文件：104.92 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 锁存器 描述：IC LATCH OCT TRANSP 3ST 20-TSSOP

ONSEMI

安森美半导体

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC LATCH OCT TRANSP 3ST 20-TSSOP

ONSEMI

安森美半导体