MC100LVEP210FAR2中文资料安森美半导体数据手册PDF规格书

描述 Description

The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode.

The LVEP210 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.

特性 Features

• 85 ps Typical Device−to−Device Skew

• 20 ps Typical Output−to−Output Skew

• VBB Output

• Jitter Less than 1 ps RMS

• 350 ps Typical Propagation Delay

• Maximum Frequency 3 GHz Typical

• The 100 Series Contains Temperature Compensation

• PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V

• Open Input Default State

• LVDS Input Compatible

• Fully Compatible with MC100EP210

• Pb−Free Packages are Available*