MC100LVEP210集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

MC100LVEP210属于集成电路（IC）的时钟缓冲器驱动器。由安森美半导体公司制造生产的MC100LVEP210时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

Description

The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode.

The LVEP210 specifically guarantees low output−to−output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.

Features

• 85 ps Typical Device−to−Device Skew

• 20 ps Typical Output−to−Output Skew

• VBB Output

• Jitter Less than 1 ps RMS

• 350 ps Typical Propagation Delay

• Maximum Frequency 3 GHz Typical

• The 100 Series Contains Temperature Compensation

• PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V

• Open Input Default State

• LVDS Input Compatible

• Fully Compatible with MC100EP210

• Pb−Free Packages are Available*