MC100LVEP111中文资料2.5 V / 3.3 V 2:1:10 差分 ECL/PECL/HSTL 时钟/数据扇出缓冲器数据手册ONSEMI规格书

描述 Description

The MC100LVEP111 is a low skew 2:1:10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP111 is operating under PECL conditions.The LVEP111 specifically guarantees low output-to-output skew.Optimal design, layout, and processing minimize skew within a device and from device to device.To ensure tightest skew, both sides of differential outputs identically terminate into 50 ohms even if only one side is being used. When fewer than all ten pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a single side are used, then leave these outputs open (unterminated). This will maintain minimum output skew. Failure to do this will result in a 10-20 ps loss of skew margin (propagation delay) in the output(s) in use.

特性 Features

• 85 ps Typical Device-to-Device Skew
• 20 ps Typical Output-to-Output Skew
• Jitter Less than 1 ps RMS
• Additive RMS Phase Jitter: 60fs @156.25MHz, Typical
• Maximum Frequency >3 Ghz Typical
• VBB Output
• 430 ps Typical Propagation Delay
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
• Open Input Default State
• LVDS Input Compatible

应用 Application

• General purpose clock and data distribution for Networking, ATE and Computing

简介

MC100LVEP111属于集成电路（IC）的时钟缓冲器驱动器。由ONSEMI制造生产的MC100LVEP111时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。