3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

文件：76.11 Kbytes 页数：8 Pages

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3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes 页数：11 Pages

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ECL D 类触发器，带重置输入和差分时钟

The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and • 350ps Typical Propagation Delay\n• Maximum Frequency > 3 Ghz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Pb-Free Packages are Available;

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3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

文件：76.11 Kbytes 页数：8 Pages

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安森美半导体

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

文件：76.11 Kbytes 页数：8 Pages

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安森美半导体

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

文件：76.11 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

文件：76.11 Kbytes 页数：8 Pages

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Evaluation Board Manual for High Frequency SOIC 8

文件：202.47 Kbytes 页数：20 Pages

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3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes 页数：11 Pages

ONSEMI

安森美半导体