MC100EP51

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description TheMC10/100EP51isadifferentialclockDflip−flopwithreset.ThedeviceisfunctionallyequivalenttotheEL51andLVEL51devices. Features •350psTypicalPropagationDelay •MaximumFrequency>3GHzTypical •PECLModeOperatingRange:VCC=3.0Vto5.5VwithVEE=0V

MC100EP51

ECL D 类触发器，带重置输入和差分时钟; • 350ps Typical Propagation Delay\n• Maximum Frequency > 3 Ghz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Pb-Free Packages are Available\n;

The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.

MC100EP51

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

MC100EP51D

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description TheMC10/100EP51isadifferentialclockDflip−flopwithreset.ThedeviceisfunctionallyequivalenttotheEL51andLVEL51devices. Features •350psTypicalPropagationDelay •MaximumFrequency>3GHzTypical •PECLModeOperatingRange:VCC=3.0Vto5.5VwithVEE=0V

MC100EP51DR2

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description TheMC10/100EP51isadifferentialclockDflip−flopwithreset.ThedeviceisfunctionallyequivalenttotheEL51andLVEL51devices. Features •350psTypicalPropagationDelay •MaximumFrequency>3GHzTypical •PECLModeOperatingRange:VCC=3.0Vto5.5VwithVEE=0V

MC100EP51DT

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description TheMC10/100EP51isadifferentialclockDflip−flopwithreset.ThedeviceisfunctionallyequivalenttotheEL51andLVEL51devices. Features •350psTypicalPropagationDelay •MaximumFrequency>3GHzTypical •PECLModeOperatingRange:VCC=3.0Vto5.5VwithVEE=0V

MC100EP51DTR2

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description TheMC10/100EP51isadifferentialclockDflip−flopwithreset.ThedeviceisfunctionallyequivalenttotheEL51andLVEL51devices. Features •350psTypicalPropagationDelay •MaximumFrequency>3GHzTypical •PECLModeOperatingRange:VCC=3.0Vto5.5VwithVEE=0V

MC100EP51D

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

MC100EP51D

Evaluation Board Manual for High Frequency SOIC 8

MC100EP51DG

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock