3.3V / 5VECL 6-Bit Differential Register with Master Reset

文件：91.53 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

文件：124.16 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

具有主重置功能的 3.3 V / 5.0 V ECL 6 位差分寄存器

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clam • 450 ps Typical Propagation Delay\n• Maximum Frequency > 3.0 GHz Typical\n• Asynchronous Master Reset\n• 20 ps Skew Within Device, 35 ps Skew Device-To-Device\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Ope;

ONSEMI

安森美半导体

3.3V / 5VECL 6-Bit Differential Register with Master Reset

文件：91.53 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

文件：124.16 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

ECL 6-Bit Differential Register

文件：114.23 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5VECL 6-Bit Differential Register with Master Reset

文件：91.53 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

文件：124.16 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

文件：124.16 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

3.3V / 5VECL 6-Bit Differential Register with Master Reset

文件：91.53 Kbytes 页数：10 Pages

ONSEMI

安森美半导体