MC100EP451

具有主重置功能的 3.3 V / 5.0 V ECL 6 位差分寄存器; • 450 ps Typical Propagation Delay\n• Maximum Frequency > 3.0 GHz Typical\n• Asynchronous Master Reset\n• 20 ps Skew Within Device, 35 ps Skew Device-To-Device\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Pb-Free Packages are Available\n;

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to EE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.

MC100EP451

3.3V / 5VECL 6-Bit Differential Register with Master Reset

MC100EP451

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

MC100EP451FA

3.3V / 5VECL 6-Bit Differential Register with Master Reset

MC100EP451FA

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

MC100EP451FAG

3.3V / 5VECL 6-Bit Differential Register with Master Reset

MC100EP451FAG

3.3V / 5V ECL 6?묪it Differential Register with Master Reset

MC100EP451FAG

ECL 6-Bit Differential Register

MC100EP451FAR2

3.3V / 5VECL 6-Bit Differential Register with Master Reset

MC100EP451FAR2

3.3V / 5V ECL 6?묪it Differential Register with Master Reset