MC100EP140中文资料相位频率检测器，3.3 V，ECL数据手册ONSEMI规格书

描述 Description

The MC100EP140 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to \"compare\" an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.The device is packaged in a small outline, surface mount 8-lead SOIC package. The output of the EP140 is 400 mV, which allows faster switching time and greater bandwidth. This device can also be used in +3.3 V systems. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.More information on Phase Lock Loop operation and application can be found in AND8040.

特性 Features

• 500 ps Typical Propagation Delay
• Maximum Frequency > 2.1 Ghz Typical
• Fully Differential Internally
• Advanced High Band Output Swing of 400 mV
• Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz
• Rise and Fall Time: 100 ps Typical
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
• Open Input Default State
• Pb-Free Packages are Available

简介

MC100EP140属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的MC100EP140时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。