M74HC126中文资料四路总线缓冲器（3态）数据手册ST规格书

描述 Description

The M74HC126 is a high-speed CMOS quad buffer (3-state) fabricated with silicon gate C2MOS technology.

The device requires the 3-state control input, G, to be set high to place the output into high impedance state.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

特性 Features

• High-speed: tPD = 8 ns (typ.) at VCC = 6 V
• Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C
• High noise immunity: VNIH = VNIL = 28 % VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 6 mA (min.)
• Balanced propagation delays: tPLH ≅ tPHL
• Wide operating voltage range: VCC (opr) = 2 V to 6 V
• Pin and function compatible with 74 series 126
• ESD performance
•CDM: 1 kV
•HBM: 2 kV
•MM: 200 V

简介

M74HC126属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的M74HC126缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。