M5M4V64S40ATP-10数据手册MinebeaMitsumi中文资料规格书

描述 Description

DESCRIPTION
The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S40ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.FEATURES
- Single 3.3v±0.3v power supply
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A7
- LVTTL Interface
- Clock frequency 125MHz /100MHz
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

特性 Features

- Single 3.3v±0.3v power supply
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A7
- LVTTL Interface
- Clock frequency 125MHz /100MHz
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch