M5M4V4S40CTP-12中文资料三菱电机数据手册PDF规格书

DESCRIPTION

The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V4S40CTP achieves very high speed data rates up to 83MHz, and is suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3v±0.3v power supply

- Clock frequency 83MHz / 67MHz

- Fully synchronous operation referenced to clock rising edge

- Dual bank operation controlled by BA(Bank Address)

- /CAS latency- 1/2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Sequential and interleave burst (programmable)

- Byte control by DQMU and DQML

- Random column access

- Auto precharge / All bank precharge controlled by A8

- Auto and self refresh

- 1024 refresh cycles /16.4ms

- LVTTL Interface

- 400-mil, 50-pin Thin Small Outline Package

(TSOP II) with 0.8mm lead pitch