M5M4V4405CTP-7中文资料三菱电机数据手册PDF规格书

DESCRIPTION

This is a family of 1048576-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential.

The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs.

Multiplexed address inputs permit both a reduction in pins and an increase in system densities.

Self or extended refresh current is low enough for battery back-up application.

FEATURES

● Standard 26 pin SOJ, 26 pin TSOP(II)

● Single 3.3V±0.3V supply

● Low stand-by power dissipation

CMOS lnput level .................................................1.8mW(Max)*

CMOS lnput level ................................................180µW(Max)

● Low operating power dissipation

M5M4V4405Cxx-6, -6S .....................................288.0mW (Max)

M5M4V4405Cxx-7, -7S ....................................252.0mW (Max)

● Self refresh capabiility*

Self refresh current ..............................................100µA(max)

● Extended refresh capability*

Extended refresh current ....................................100µA(max)

● Hyper-page mode (1024-bit random access), Read-modify- write,

RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR

self refresh(-6S,-7S) capabilities.

● Early-write mode and OE and W to control output buffer impedance

● 1024 refresh cycles every 16.4ms (A0~A9)

● 1024refresh cycle every128ms (A0~A9)*

*: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S: option) only

APPLICATION

Lap top personal computer,Solid state disc, Microcomputer memory, Refresh memory for CRT