M54HC76F1R中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The M54/74HC76 is a high speed CMOSDUAL J-K FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Depending on with the logic level at the J and K inputs this device changes state on the negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

■ HIGH SPEED fMAX = 65 MHz (TYP.) AT VCC = 5 V

■ LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT 25 °C

■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

■ SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.)

■ BALANCED PROPAGATION DELAYS tPLH = tPHL

■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.)

■ WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V

■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS76