256M Synchronous DRAM

DESCRIPTION M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT

文件：694.87 Kbytes 页数：49 Pages

MITSUBISHI

三菱电机

256M Synchronous DRAM

DESCRIPTION M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT

文件：694.87 Kbytes 页数：49 Pages

MITSUBISHI

三菱电机

256M Synchronous DRAM

DESCRIPTION M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40

文件：431.86 Kbytes 页数：51 Pages

MITSUBISHI

三菱电机

256M Synchronous DRAM

DESCRIPTION M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT

文件：694.87 Kbytes 页数：49 Pages

MITSUBISHI

三菱电机