64M bit Synchronous DRAM

DESCRIPTION The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of C

文件：674.36 Kbytes 页数：52 Pages

MITSUBISHI

三菱电机

64M bit Synchronous DRAM

DESCRIPTION The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of C

文件：674.36 Kbytes 页数：52 Pages

MITSUBISHI

三菱电机