Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access

文件：852.79 Kbytes 页数：50 Pages

agere

Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access

文件：852.79 Kbytes 页数：50 Pages

agere

Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access

文件：852.79 Kbytes 页数：50 Pages

agere

1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

文件：377.93 Kbytes 页数：12 Pages

Maxim

美信

1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

General Description The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single-ended

文件：377.93 Kbytes 页数：12 Pages

Maxim

美信