LS1021AXE7MQB中文资料恩XP数据手册PDF规格书

特性 Features

• Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture

• LS1021A contains a dual-core Cortex-A7. Each core includes:

– 32 KB L1 Instruction Cache (ECC protection)

– 32 KB L1 Data Cache (ECC protection)

– NEON co-processor

– Floating Point (FPU)

– QorIQ Trust Architecture and Arm TrustZone®

• Snoop Control Unit (SCU)

• 512 KB unified I/D L2 Cache (ECC protection)

• Hierarchical interconnect fabric

– The platform has a single 128-bit AMBA 4 AXI Coherency Extensions (ACE) master port, which connects to CCI-400 Interconnect.

• One 8/16/32-bit DDR3L/DDR4 SDRAM memory controllers

– ECC and interleaving support

• VeTSEC Ethernet complex

– Up to 3x Gigabit Ethernet

– MII, RMII, RGMII, and SGMII support

– QoS, lossless flow control, and IEEE® 1588

• Up to 4 SerDes lanes for high-speed peripheral interfaces

– Two PCI Express Gen2 controllers

– One Serial ATA 3.0 (SATA 1.5, 3.0, 6.0 Gbps) controller

– Two SGMII interfaces supporting 1000 Mbps

• Integrated audio block

– Four synchronous audio interfaces (SAI)

– I2S, AC97, and Codec/DSP interfaces

– Sony/Philips Digital Interconnect Format (S/PDIF)

– Asynchronous Sample Rate Converter (ASRC)

• Additional peripheral interfaces

– One high-speed USB 3.0 controller with integrated PHY

– One high-speed USB 2.0 controller with ULPI

– Enhanced secure digital host controller (eSDHC/MMC/eMMC)

– Three I2C controllers

– Four FlexCAN modules

– FlexTimer/PWM

– SPI interface

– QuadSPI controller

– Two DUARTs

– Six LPUART interfaces

– Integrated flash controller supporting NAND and NOR flash

– Display controller unit (2D-ACE) 24-bit RGB (12-bit DDR pin interface)

– TDM interface

– Four GPIO controllers supporting up to 109 general purpose I/O signals

– One 4-channel qDMA controller and one eDMA controller

– Global programmable interrupt controller (GIC)

– Thermal monitoring unit (TMU)

• QUICC Engine ULite block

– 32-bit RISC controller for flexible support of the communications peripherals

– Serial DMA channel for receive and transmit on all serial channels

– Two universal communication controllers (TDM and HDLC) supporting 64 multichannels, each running at 64 Kbps

• 525 FC-PBGA package, 19 mm x 19 mm