LPC2367FBD100中文资料Arm7™，带512 kB闪存、58 kB SRAM、以太网，以及10位ADC数据手册恩XP规格书

描述 Description

The LPC2367FBD100 is a Arm7 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 72 MHz. Features include up to 256 kB of flash memory, up to 58 kB of RAM, Ethernet MAC, DMA controller, 4 UARTs, 3 SSP/SPI, 3 I2C, I2S, 8-channel 10-bit ADC, 10-bit DAC, 2 PWM, 4 general purpose timers, low power Real-Time Clock with separate battery supply, and up to 70 general purpose I/O pins. The LPC23xx are pin-compatible to the LPC176x Cortex-M3 series.

特性 Features

• Arm7TDMI-S™ processor, running at up to 72 MHz
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP)
• 32 kB of SRAM on the Arm local bus for high performance CPU access
• 8 kB SRAM for general purpose DMA use also accessible by the USB
• 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM
• Dual Advanced High-performance Bus (AHB) system
• Advanced Vectored Interrupt Controller (VIC)
• General Purpose DMA controller (GPDMA) on AHB
• Ethernet MAC with associated DMA controller
• Four UARTs with fractional baud rate generation
• SPI controller
• Two SSP controllers, with FIFO and multi-protocol capabilities
• Three I2C-bus interfaces
• I2S (Inter-IC Sound) interface for digital audio input or output
• SD/MMC memory card interface
• 70 general purpose I/O pins with configurable pull-up/down resistors
• 10-bit ADC with input multiplexing among 6 pins
• 10-bit DAC
• Four general purpose timers/counters with a total of 8 capture inputs
• One PWM/timer block with support for three-phase motor control
• Real-Time Clock (RTC)
• 2 kB SRAM powered from the RTC power pin
• WatchDog Timer (WDT).
• Standard Arm test/debug interface for compatibility with existing tools
• Emulation trace module supports real-time trace
• Single 3.3 V power supply (3.0 V to 3.6 V)
• Four reduced power modes: idle, sleep, power-down, and deep power-down
• Four external interrupt inputs configurable as edge/level sensitive
• Processor wake-up from Power-down mode via any interrupt
• Two independent power domains allow fine tuning of power consumption
• Each peripheral has its own clock divider for further power saving
• Brownout detect with separate thresholds for interrupt and forced reset
• On-chip power-on reset
• On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz
• 4 MHz internal RC oscillator trimmed to 1 % accuracy
• On-chip PLL

应用 Application

工业控制
医疗系统
协议转换器
通信