LPC18S10FET100数据手册恩XP中文资料规格书

描述 Description

The LPC18S10FET100 is a Arm Cortex-M3 based microcontroller with securityfeatures for embedded applications. The Arm Cortex-M3 is a next generation core thatoffers system enhancements such as low power consumption, enhanced debug features,and a high level of support block integration.
The LPC18S10FET100 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.
The LPC18S10FET100 includes 136 kB of on-chip SRAM, security features withAES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM(SCTimer/PWM) subsystem, an externalmemory controller, and multiple digital and analog peripherals.

特性 Features

• Processor core
• Arm Cortex-M3 processor, running at frequencies of up to 180 MHz.
• Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
• Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Non-maskable Interrupt (NMI) input.
• JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
• Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
• System tick timer.
• On-chip memory
• 136 kB SRAM for code and data use.
• Multiple SRAM blocks with separate bus access.
• 64 kB ROM containing boot code and on-chip software drivers.
• 64 bit One-Time Programmable (OTP) memory for general-purpose use.
• Two banks (256 bit total) One-Time Programmable (OTP) memory for AES keystorage One bank can store an encrypted key for decoding the boot image.
• AES engine for encryption and decryption of the boot image and data with DMAsupport and programmable via a ROM-based API.
• Clock generation unit
• Crystal oscillator with an operating range of 1 MHz to 25 MHz.
• 12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature andvoltage.
• Ultra-low power RTC crystal oscillator.
• Three PLLs allow CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. The second PLL is dedicated to the High-speed USB, thethird PLL can be used as audio PLL.
• Clock output.
• Configurable digital peripherals:
• State Configurable Timer (SCTimer/PWM) subsystem on AHB.
• Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1.
• Serial interfaces
• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to52 MB per second.
• Four 550 UARTs with DMA support: one UART with full modem interface; oneUART with IrDA interface; three USARTs support UART synchronous mode and asmart card interface conforming to ISO7816 specification.
• Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge.
• Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport.
• One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/Opins conforming to the full I2C-bus specification. Supports data rates of up to1 Mbit/s.
• One standard I²C-bus interface with monitor mode and standard I/O pins.
• Two I²S interfaces with DMA support, each with one input and one output.
• Digital peripherals
• External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices.
• Secure Digital Input Output (SD/MMC) card interface.
• Eight-channel General-Purpose DMA controller can access all memories on theAHB and all DMA-capable AHB slaves.
• Up to 49 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors.
• GPIO registers are located on the AHB for fast access. GPIO ports have DMAsupport.
• Up to eight GPIO pins can be selected from all GPIO pins as edge and levelsensitive interrupt sources.
• Two GPIO group interrupt modules enable an interrupt based on a programmablepattern of input states of a group of GPIO pins.
• Four general-purpose timer/counters with capture and match capabilities.
• Repetitive Interrupt timer (RI timer).
• Windowed watchdog timer.
• Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytesof battery powered backup registers.
• Alarm timer; can be battery powered.
• Analog peripherals
• One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
• Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.Up to eight input channels per ADC.
• Unique ID for each device.
• Power
• Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator forthe core supply and the RTC power domain.
• RTC power domain can be powered separately by a 3 V battery supply.
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down.
• Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals.
• Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery powered blocks in the RTCpower domain.
• Brownout detect with four separate thresholds for interrupt and forced reset.
• Power-On Reset (POR).
• Available as TFBGA100package.

应用 Application

通信集线器
汽车售后市场
电源管理
消费者医疗设备
嵌入式音频应用
工业控制
工业自动化
白色家电