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LMK3H2104A02LRGER中文资料德州仪器数据手册PDF规格书

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厂商型号

LMK3H2104A02LRGER

功能描述

LMK3H2104 4-Output PCIe Gen 1-7 Compliant Low jitter General Purpose BAW Clock Generator

丝印标识

3H2104LA02

封装外壳

VQFN(RGE)

文件大小

2.75251 Mbytes

页面数量

53

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-10-31 23:00:00

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LMK3H2104A02LRGER价格和库存,欢迎联系客服免费人工找货

LMK3H2104A02LRGER规格书详情

1 Features

• Integrated BAW resonator

– No need for external XTAL/XO

• Flexible output frequency

– 2 fraction output dividers (FOD), individual

channel dividers

– Up to 400MHz output frequency

• Flexible output format

– 1.2/1.8/2.5/3.3V LVCMOS

– DC- or AC-coupled LVDS

– LP-HCSL with programmable swing. LVPECL,

CML and other formats can be derived from

LP-HCSL

• Very low jitter

– 61fs max PCIe Gen 5 CC with SSC jitter

– 36.4fs max PCIe Gen 6 CC with SSC jitter

– 25.5fs max PCIe Gen 7 CC with SSC jitter

• PCIe Gen 1 to Gen 7 compliant

• Configurable SSC

– Programmable -0.05% to -3% down spread and

±0.025% to ±1.5% center spread, or preset

-0.1%, -0.25%, -0.3% and -0.5% down spread

• 1 input (LMK3H2104) that can be bypassed to any

output

• 5ms max startup time

• Fail-safe input pins can be pulled high when

device power is off

• Flexible power supply

– Each VDD pin can be independently connected

to = 1.8, 2.5 or 3.3V

– Each VDDO pin can be independently

connected set to 1.8, 2.5 or 3.3V

• -40 to 105°C ambient temperature

2 Applications

• High Performance Computing Server Motherboard

• NIC, SmartNIC and Hardware Acceleration

• PCIe Gen 1 to Gen 7 clock generation

• General purpose clock generation and XO/XTAL

replacement

3 Description

LMK3H2104 is a BAW-based clock generator that

does not require any external XTAL or XO. The device

can be used as PCIe clock generator or general

purpose clock generator. The 2 FODs (Fractional

Output Divider) provide frequency flexibility, low power

and low jitter at the same time.

LMK3H2104 has up to 4 differential outputs plus

2 LVCMOS outputs or up to 10 LVCMOS outputs.

The device also has one clock input. The clock

input provides clock multiplexing and buffering ability.

Each output bank can independently select any clock

source.

The GPI and GPIO pins provide additional control

flexibility. These pins can be configured as individual

OE, grouped OE, I2C address selection, OTP page

selection, PWRGD/PWRDN#, status output and other

functions.

The device supports one-time programmable (OTP)

non-volatile memory which can be customized and

factory preprogrammed.

供应商 型号 品牌 批号 封装 库存 备注 价格
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