丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

文件：1.96898 Mbytes 页数：33 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

文件：1.96898 Mbytes 页数：33 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

丝印：LMK1D1204P；Package：VQFN；LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器