丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP(P)；LFx98x Monolithic Sample-and-Hold Circuits

1 Features 1• Operates from ±5-V to ±18-V Supplies • Less than 10-μs Acquisition Time • Logic Input Compatible With TTL, PMOS, CMOS • 0.5-mV Typical Hold Step at Ch = 0.01 μF • Low Input Offset • 0.002% Gain Accuracy • Low Output Noise in Hold Mode • Input Characteristics Do Not Change

文件：3.23114 Mbytes 页数：41 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP；LFx98x Monolithic Sample-and-Hold Circuits

文件：3.53831 Mbytes 页数：38 Pages

TI

德州仪器

丝印：LF398N；Package：PDIP；LFx98x Monolithic Sample-and-Hold Circuits

文件：3.53831 Mbytes 页数：38 Pages

TI

德州仪器