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K4H511638D-UCSLASHLA2中文资料三星数据手册PDF规格书
K4H511638D-UCSLASHLA2规格书详情
Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II Pb-Free package
• RoHS compliant
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
24+ |
FBGA60 |
43200 |
郑重承诺只做原装进口现货 |
询价 | ||
SAMSUNG/三星 |
24+ |
BGA |
9600 |
原装现货,优势供应,支持实单! |
询价 | ||
SAMSUNG |
22+ |
TSOP |
8000 |
原装正品支持实单 |
询价 | ||
SAMSUNG/三星 |
21+ |
BGA |
10000 |
原装现货假一罚十 |
询价 | ||
SAMSUNG/三星 |
0852+ |
FBGA60 |
13440 |
只做原装正品 |
询价 | ||
SAMSUNG |
23+ |
BGA |
8650 |
受权代理!全新原装现货特价热卖! |
询价 | ||
SAMSUNG |
25+23+ |
FBGA60 |
36084 |
绝对原装正品全新进口深圳现货 |
询价 | ||
SAMSUNG/三星 |
23+ |
FBGA |
50000 |
全新原装正品现货,支持订货 |
询价 | ||
SAMSUNG/三星 |
23+ |
BGA |
98900 |
原厂原装正品现货!! |
询价 | ||
SAMSUNG/三星 |
2023+ |
FBGA60 |
13440 |
原厂全新正品旗舰店优势现货 |
询价 |