Multilayer Chip Capacitors

文件：323.06 Kbytes 页数：17 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

Multilayer Chip Capacitors

文件：323.06 Kbytes 页数：17 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

Multilayer Chip Capacitors

文件：323.06 Kbytes 页数：17 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

Multilayer Chip Capacitors

文件：323.06 Kbytes 页数：17 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

ULTIMATE CRIMPING ACCURACY

文件：276.98 Kbytes 页数：2 Pages

GREENLEE

丝印：K05WY；Package：TSSOP8；Low-power dual operational amplifier

Description This circuit consists of two independent, high gain operational amplifiers (op amps) that have frequency compensation implemented internally. They are designed specifically for automotive and industrial control systems. The circuit operates from a single power supply over a wide ra

文件：1.10942 Mbytes 页数：28 Pages

STMICROELECTRONICS

意法半导体

丝印：K05318BQ1；Package：VQFN；LMK05318B-Q1 Ultra-Low Jitter Network Synchronizer and Clock Generator With BAW VCO for Automotive and Industrial Applications

1 Features • AEC-Q100 qualified for automotive applications – Temperature grade 2: –40°C to 105°C • Ultra-low jitter BAW VCO based Ethernet clocks – 50fs typical RMS jitter at 312.5MHz – 60fs typical RMS jitter at 156.25MHz • One high-performance Digital Phase-Locked Loop (DPLL) paired with

文件：3.5012 Mbytes 页数：89 Pages

TI

德州仪器

丝印：K05318BQ1；Package：VQFN；LMK05318B-Q1 Ultra-Low Jitter Network Synchronizer and Clock Generator With BAW VCO for Automotive and Industrial Applications

1 Features • AEC-Q100 qualified for automotive applications – Temperature grade 2: –40°C to 105°C • Ultra-low jitter BAW VCO based Ethernet clocks – 50fs typical RMS jitter at 312.5MHz – 60fs typical RMS jitter at 156.25MHz • One high-performance Digital Phase-Locked Loop (DPLL) paired with

文件：3.5012 Mbytes 页数：89 Pages

TI

德州仪器

丝印：K05318A32500；Package：VQFN(RGZ)；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：2.20662 Mbytes 页数：86 Pages

TI

德州仪器

丝印：K05318A32500；Package：VQFN(RGZ)；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：2.20662 Mbytes 页数：86 Pages

TI

德州仪器