LMK05318BTRGZTQ1中文资料德州仪器数据手册PDF规格书

1 Features

• AEC-Q100 qualified for automotive applications

– Temperature grade 2: –40°C to 105°C

• Ultra-low jitter BAW VCO based Ethernet clocks

– 50fs typical RMS jitter at 312.5MHz

– 60fs typical RMS jitter at 156.25MHz

• One high-performance Digital Phase-Locked Loop

(DPLL) paired with two Analog Phase Locked

Loops (APLLs):

– Programmable DPLL loop bandwidth

– < 1-ppt DCO frequency adjustment step size

• Two differential or single-ended DPLL inputs

– 1Hz (1-PPS) to 800MHz input frequency

– Digital holdover and hitless switching

• Eight differential outputs with programmable

HSDS/LVPECL, LVDS, HSCL and 1.8V LVCMOS

output formats.

– Up to six different output frequencies

– 1Hz (1-PPS) to 1250MHz output frequency

– PCIe Gen 1 to 6 compliant

• I2C or SPI register control bus

• EEPROM for custom system configurations on

start-up

2 Applications

• Jitter Cleaning, Wander Attenuation, and

Reference Clock Generation for 56G/112G PAM-4

PHYs, ASICs, FPGAs, SoCs, and Processors

• Advanced driver assistance systems (ADAS) -

Sensor Fusion

• Infotainment & Cluster - Automotive Head Unit -

eAVB

• Body electronics & lighting

– Zonal & body domain controller

• SyncE (G.8262), SONET/SDH (Stratum 3/3E,

G.813, GR-1244, GR-253), IEEE 1588 PTP

secondary clock

• Test and measurement

• Medical imaging

3 Description

The LMK05318B-Q1 is high-performance network

synchronizer clock device that provides jitter cleaning,

clock generation, advanced clock monitoring, and

superior hitless switching performance to meet the

stringent timing requirements of communications

infrastructure and industrial applications. The ultra-low

jitter and high power supply noise rejection (PSNR)

of the device can reduce bit error rates (BER) in highspeed

serial links.