In-System Programmable 3.3V SuperWIDE™ High Density PLD

Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 24000 PLD Gates / 512 Macrocells — Up to 256 I/O Pins — 512 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocel

文件：275.92 Kbytes 页数：25 Pages

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In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

文件：242.23 Kbytes 页数：22 Pages

LATTICE

莱迪思