ISLA222S25数据手册集成电路（IC）的模数转换器（ADC）规格书PDF

描述 Description

The ISLA222S is a series of low-power, high-performance, dual-channel 12-bit, analog-to-digital converters. Designed with FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The ISLA222S is part of a pin-compatible family of 12- and 14-bit dual-channel A/Ds with maximum sample rates ranging from 125MSPS to 250MSPS and shares the same analog core as Intersil's proven ISLA222P series of ADCs. The family minimizes power consumption while providing state of the art dynamic performance, offering an optimal performance vs power trade-off.
Differentiating the ISLA222S from the ISLA222P is its highly configurable, JESD204B-compliant, high-speed serial output link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It can be configured to use one, two, or three lanes to transmit the conversion data, allowing for flexibility in the receiver design. The SERDES transmitter also provides deterministic latency and multi-chip time alignment support to satisfy an application's complex synchronization requirements.
A Serial Peripheral Interface (SPI) port allows for extensive configurability of the JESD204B transmitter including access to its built-in link and transport layer test patterns. The SPI port also provides control for numerous additional features including the fine gain and offset adjustments of the two ADC cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking.
The ISLA222S is available in a space saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40°C to +85°C).

特性 Features

• JESD204A/B high-speed data interface
• JESD204A compliant
• JESD204B device subclass 0 compliant
• JESD204B device subclass 2 compatible
• Up to 3 JESD204 output lanes running up to 4.375Gbps
• Highly configurable JESD204 transmitter
• Multiple chip time alignment and deterministic latency support (JESD204B device subclass 2)
• SPI programmable debugging features and test patterns
• 48-pin QFN 7mmx7mm package Key Specifications
• SNR at 250/200/125MSPS 70.6/71.2/71.7 dBFS fIN = 30MHz 70.3/70.7/70.9 dBFS fIN = 190MHz
• SFDR at 250/200/125MSPS 87/93/95 dBc fIN = 30MHz 84/93/86 dBc fIN = 190MHz
• Total Power Consumption: 989mW at 250MSPS

应用 Application

• Radar and satellite antenna array processing
• Broadband communications and microwave receivers
• High-performance data acquisition
• Communications test equipment
• High-speed medical imaging