128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：2.41096 Mbytes 页数：40 Pages

ISSI

矽成半导体

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：2.41096 Mbytes 页数：40 Pages

ISSI

矽成半导体

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：2.41096 Mbytes 页数：40 Pages

ISSI

矽成半导体

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：2.41096 Mbytes 页数：40 Pages

ISSI

矽成半导体