512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体

512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an

文件：2.03174 Mbytes 页数：35 Pages

ISSI

矽成半导体