4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

文件：895.21 Kbytes 页数：60 Pages

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矽成半导体

4M x 32 128Mb SYNCHRONOUS DRAM

OVERVIEW ISSIs 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. FEATURES • Clock frequency: 166, 143, 133 MHz • Fully sync

文件：895.21 Kbytes 页数：60 Pages

ISSI

矽成半导体

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TSOP86

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矽成半导体

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TSOP8

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矽成半导体

上传：深圳市胜彬电子有限公司

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TSOP

ISSI

矽成半导体

上传：深圳市吉铭电子科技有限公司