IP1725数据手册IC+中文资料规格书

描述 Description

The IP1725 is a cost effective and fully integrated single chip. It integrates a 25-port switch controller, an 3X octal PHY transceiver and SSRAM. Each of PHY transceiver complies with 802.3u specification and HP-license Auto MDI/MDIX. \r
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It supports full smart switch functions, including IGMP snooping, 4 priority queues, TOS, TCP/UDP port number priority, 802.1Q VLAN, port security, protocol filter/forwarding and bandwidth control.

特性 Features

S25 Ports 10/100Mb Ethernet Layer 2 Smart Switch\r
- Built-in 24 PHYs \r
- One MII interface\r
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Store & Forward, Share Memory Non_blocking Architecture\r
- Built-in 2.5Mb SRAM (1.75Mb for packet buffer)\r
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- Max. length 1664B\r
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Wire-speed Operation On Every Port\r
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Head Of Line Blocking Prevention\r
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Flow Control Support\r
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- 802.3x compliant flow control in full duplex\r
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- Collision/Carrier_snese based backpressure in half duplex\r
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Internal 8K MAC Address Entities\r
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- CRC/direct hashing algorithm\r
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- Aging timer programmable (55s~251.6hr) < 4 %\r
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- Wire speed address learning and resolution\r
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- CPU accessible for security and static MAC\r
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- Learning enable/disable\r
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Sniffer Function Support (in/out/in+out)\r
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IGMP Snooping Support\r
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- Version 1 , 2\r
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- Snooping by Switch ASIC or external CPU\r
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Two Trunk Group Support\r
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- Two trunk groups, each trunk has 4 ports (max)\r
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- The ports belong to trunk group are configurable\r
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- Load balance based on (Port ID, DA , SA, DA/SA)\r
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- Link fault recovery\r
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VLAN (32 VLAN groups)\r
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- Port based\r
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- Tagged based\r
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- Tag remove/add/modify support\r
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- Special TAG support\r
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- Protected VLAN\r
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- Q-in-Q (double tag) support\r
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Class Of Service (CoS) Support\r
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- Port based\r
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- 802.1Q priority based tagged based\r
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- IP TOS based (IPv4/IPv6)\r
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- TCP/UDP port number based\r
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- Destination MAC address based\r
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- IP address based\r
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- 4 levels per port\r
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- WRR/FIFS/SP/SP+WRR\r
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- ACL based\r
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Broadcast Storm Control\r
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- Broadcast rate control per port selectable\r
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- With option to drop all ARP to CPU\r
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- Also has ARP and ICMP storm control\r
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Multi-cast/unknown DA frames can be counted\r
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Port Security\r
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- MAC based\r
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- IP(DIP/SIP) based (IPv4 32 bit only\r
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- TCP/UDP port based\r
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- Port based\r
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Bandwidth Control\r
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- 32K bpsxN 256 levels\r
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- 512K bpsxN 256 levels\r
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- With flow control/Without flow control\r
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- WAN port control support\r
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Support SMI Interface Auto-polling\r
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- Speed, Duplex, Flow control, Link\r
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- CPU accessible (interrupt support)\r
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- CPU R/W PHY register\r
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Out Queue Aging Function\r
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- From 100 ms to 6.3 sec selectable\r
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Spanning Tree Protocol Port State Support\r
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- Discard/Block/Learning/Forwarding four states support\r
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- Forwarding STP frame to CPU port\r
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- RSTP support\r
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Support 16 ACL Entities Based On\r
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- Ingress port or VLAN\r
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- Destination/Source IP (specific or range)\r
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- TCP/UDP Destination/Source port number (specific, > 1023, <=1023)\r
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- Forwarding STP frame to CPU port\r
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- Action : forward, to CPU, drop, priority, Q-in-Q tag\r
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Configuration\r
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- Pin initial setting\r
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- 2-wire serial interface for configuration EEPROM\r
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- 2-wire serial interface for low cost smart system application\r
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Per Port 2 Counter (32 bit x 2) Selectable\r
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- RX/TX packet count\r
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- CRC error packet count\r
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- Drop packet count\r
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- Collision count\r
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LED\r
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- Direct mode\r
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- 2-wire serial mode\r
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Support Auto Test Function For Mass-production\r
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- Auto generate test frames\r
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- Shown the result on LED output\r
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Interrupt Pin For PHY Mode/Link/SMI R/W\r
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- Complete notification\r
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Build-in SRAM Self Test (BIST)\r
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Build-in Oscillator Circuit, Only One 25 MHz Crystal Needed\r
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IO Voltage Selectable (3 groups)\r
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90 nm Process, 208 Pin EDHS-QFP