IP1717数据手册IC+中文资料规格书

描述 Description

The IP1717 is a cost effective and fully integrated single chip. It integrates a 17-port switch controller, an octal PHY transceiver and SSRAM. Each of PHY transceiver complies with 802.3u specification and HP-license Auto MDI/MDIX. \r
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The IP1717 also provides a 3S-MII interface to connect an octal PHY for a 16-port dumb switch application and a MII interface for a smart/management switch application.\r
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In addition, it supports full smart switch functions, including IGMP snooping, 4 priority queues, TOS, TCP/UDP port number priority, 802.1Q VLAN, port security, protocol filter/forwarding and bandwidth control.

特性 Features

Built in 8 internal PHY, 8 SS-SMII (SMII), and one MII\r
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Built in 1.625Mb RAM\r
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Support packet length up to 1600 Bytes\r
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Store & forward, share memory, non-blocking architecture \r
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Support flow control\r
- 802.3x in full duplex \r
- Collision/Carrier_sense based backpressure in half duplex\r
Provide up to 4K MAC address entries\r
- CRC/ direct hashing algorithm \r
- Programmable aging timer (55s~1812070.4s)\r
- Wire speed address learning and resolution\r
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- CPU accessible for security and static MAC\r
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- Learning enable/disable\r
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- IP filter \r
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Support Sniffer function (in, out, in & out) \r
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Support IGMP snooping function Version 1,2\r
- Support up to 2 trunk groups \r
- (Port 0~3, port 4~7)\r
- Load balance based on (port, DA, SA, DA / SA)\r
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Support VLAN\r
- Port based VLAN \r
- Tag based VLAN based on Ports & VIDs\r
- Add/ remove/ modify tag\r
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Support Class of Service\r
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- Port based CoS function\r
- 802.1Q priority tag based\r
- IP TOS based (IPv4/IPv6)\r
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- TCP/UDP port based\r
- 4 queues for per port\r
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- WRR/ FIFS/ SP algorithm \r
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Broadcast storm control support\r
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- Broadcast rate control per port\r
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- Block broadcast packet that not belongs to ARP or IPv4 packet to CPU port\r
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Support port security\r
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- MAC address based\r
- IP address based\r
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Supports Bandwidth control\r
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- 255 configurable levels for P0~P16, (from 32kbps to 7.96 Mbps) for low bandwidth\r
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- 255 configurable levels for P0-P16 (from 512kbps to 100 Mbps) for high bandwidth \r
- With/without flow control\r
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Support SMI auto-polling function\r
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- Poll for speed, duplex, flow control, and link\r
- CPU accessible (interrupt support)\r
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CPU R/W PHY registers\r
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Support SS_SMII and SMII mode\r
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Support 4 port states for Spanning Tree protocol\r
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- Discarding/Blocking/learning/ forwarding \r
- Forward BPDU to CPU port\r
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Captures specific packet to CPU port\r
BPDU, LACP, 802.1X, GMRP, GVRP, ARP\r
ICMP, IGMP, TCP, UDP, OSPF, other IP protocols\r
- Packets with specific TCP/UDP port number\r
Flexible PHY address setting for CPU \r
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Support three Configuration modes\r
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- Pin initial setting\r
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- 2 wire serial interface for EEPROM \r
- 2 wire serial interface for CPU\r
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Statistic counters for each port\r
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- RX/TX packet count\r
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- CRC error packet count \r
- Drop packet count\r
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- Collision count\r
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Support force link without SMI for Port16\r
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Support Non association port\r
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Support port based address flush \r
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Support LED functions (for p0~p7)\r
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- Support 2 bit serial,3 bit serial, and 3 bit bi color mode\r
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- Support direct LED mode for Link/Activity, speed, duplex states \r
- Support bi color direct LED mode\r
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Only one 25MHz crystal is needed\r
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Adjustable IO voltage (3.3v MII1.95V SS-SMII)\r
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Programmable MAC address table through CPU interface\r
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128 pin PQFP Lead free package