IP101A中文资料PHY 10/100M Single Chip Fast Ethernet Transceiver数据手册IC+规格书

描述 Description

IP101A is an IEEE 802.3/802.3u compliant single-port Fast Ethernet Transceiver for both 100Mbps and 10Mbps operations. It supports Auto MDI/MDIX function to simplify the network installation and reduce the system maintenance cost. To improve the system performance, IP101A provides a hardware interrupt pin to indicate the link, speed and duplex status change. IP101A also provides Media Independent Interface (MII) / Serial Network Interface (SNI) or Reduced Media Independent Interface (RMII) to connect with different types of 10/100Mb Media Access Controller (MAC).

IP101A is designed to use category 5 unshielded twisted-pair cable connecting to other LAN devices.

IP101A Transceiver is fabricated with advanced CMOS technology, which the chip only requires 3.3V as power supply and consumes very low power in the Auto Power Saving mode. IP101A can be implemented as Network Interface Adapter with RJ-45 for twisted-pair connection. It can also be easily implemented into HUB, Switch, Router, Access Point.

特性 Features

10/100Mbps TX
Full-duplex or half-duplex
Supports Auto MDI/MDIX function
Fully compliant with IEEE 802.3/802.3u
Supports IEEE 802.3u auto-negotiation
Supports MII / RMII / SNI interface
IEEE 802.3 full duplex control specification
Supports Automatic Power Saving mode
Supports BaseLine Wander (BLW) compensation
Supports Interrupt function
Supports repeater mode
Single 3.3V power supply with built-in 2.5V requlator
DSP-based PHY Transceiver technology
Using either 25MHz crystal or 50MHz oscillator REF_CLK as clock source
Flexible LED display for speed, duplex, link, activity and collision
Supports flow control to communicate with other MAC through MDC and MDIO
0.25µ,CMOS technology
48-pin LQFP