EPROM/ROM Microcontrollers with
Real-Time Clock
www.maxim-ic.com
FEATURES PIN CONFIGURATIONS
80C52 Compatible TOP VIEW
8051 Instruction-Set Compatible
Four 8-Bit I/O Ports 7 1 47
Three 16-Bit Timer/Counters 46
256 Bytes Scratchpad RAM 8
Large On-Chip Memory DALLAS
16kB EPROM (OTP) DS87C530
1kB Extra On-Chip SRAM for MOVX DS83C530
ROMSIZE Features 20 34
Selects Effective On-Chip ROM Size from
0 to 16kB 21 33
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software PLCC， WINDOWED CLCC
Useful as Boot Block for External Flash
39 27
Nonvolatile Functions
On-Chip Real-Time Clock with Alarm Interrupt 40 26
Battery Backup Support of 1kB SRAM
DALLAS
High-Speed Architecture DS87C530
4 Clocks/Machine Cycle (8051 = 12) DS83C530
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns 52 14
Dual Data Pointer
Optional Variable Length MOVX to Access 1 13
Fast/Slow RAM /Peripherals
TQFP
Power Management Mode
Programmable Clock Source Saves Power The High-Speed Microcontroller Users Guide must
Runs from (crystal/64) or (crystal/1024) be used in conjunction with this data sheet. Download it
Provides Automatic Hardware and_Software Exit at: www.maxim-ic.com/microcontrollers.
EMI Reduction Mode Disables ALE
Two Full-Duplex Hardware Serial Ports
High Integration Controller Includes:
Power-Fail Reset
Early-Warning Power-Fail Interrupt
Programmable Watchdog Timer
14 Total Interrupt Sources with Six External
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata， click here: www.maxim-ic.com/errata.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
ORDERING INFORMATION
PART TEMP RANGE MAX CLOCK PIN-PACKAGE
SPEED
DS87C530-QCL 0C to +70C (MHz) 52 PLCC
DS87C530-QCL+ 0C to +70C 33 52 PLCC
DS87C530-QNL -40C to +85C 33 52 PLCC
DS87C530-QNL+ -40C to +85C 33 52 PLCC
DS87C530-KCL*_ 0C to +70C 33 52 Windowed CLCC
DS87C530-ECL 0C to +70C 33 52 TQFP
DS87C530-ECL+ 0C to +70C 33 52 TQFP
DS87C530-ENL -40C to +85C 33 52 TQFP
DS87C530-ENL+ -40C to +85C 33 52 TQFP
DS83C530-QCL 0C to +70C 33 52 PLCC
DS83C530-QCL+ 0C to +70C 33 52 PLCC
DS83C530-QNL -40C to +85C 33 52 PLCC
DS83C530-QNL+ -40C to +85C 33 52 PLCC
DS83C530-ECL 0C to +70C 33 52 TQFP
DS83C530-ECL+ 0C to +70C 33 52 TQFP
DS83C530-ENL -40C to +85C 33 52 TQFP
DS83C530-ENL+ -40C to +85C 33 52 TQFP
33
+ Denotes a lead(Pb)-free/RoHS-compliant device.
*_The windowed ceramic LCC package is intrinsically lead(Pb) free.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
DETAILED DESCRIPTION
The DS87C530/DS83C530 EPROM/ROM microcontrollers with a real-time clock (RTC) are 8051-
compatible microcontrollers based on the Dallas Semiconductor high-speed core. They use 4 clocks per
instruction cycle instead of the 12 used by the standard 8051. They also provide a unique mix of
peripherals not widely available on other processors. They include an on-chip RTC and_battery backup
support for an on-chip 1k x 8 SRAM. The new Power Management Mode allows software to select_
reduced power operation while still processing.
A combination of high-performance microcontroller core， RTC， battery-backed SRAM， and_power
management makes the DS87C530/DS83C530 ideal for instruments and_portable applications. They also
provide several peripherals found on other Dallas high-speed microcontrollers. These include two
independent serial ports， two data pointers， on-chip power monitor with brownout detection and_a
watchdog timer.
Power Management Mode (PMM) allows software to select_a slower CPU clock. While default operation
uses four clocks per machine cycle， the PMM runs the processor at 64 or 1024 clocks per cycle. There is a
corresponding drop_in power consumption when the processor slows.
The EMI reduction feature allows software to select_a reduced emission mode. This disables the ALE
signal when it is unneeded.
The DS83C530 is a factory mask ROM version of the DS87C530 designed for high-volume， cost-
sensitive applications. It is identical in all respects to the DS87C530， except that the 16kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C530 will apply to
the DS83C530， with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.
Note: The DS87C530/DS83C530 are monolithic devices. A user must supply an external battery or super
cap and_a 32.768kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM.
The DS87C530/DS83C530 provide all the support and_switching circuitry needed to manage these
resources.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Figure 1. Block Diagram
DS87C530/
DS83C530
PIN DESCRIPTION
PIN NAME FUNCTION
PLCC TQFP VCC +5V Processor Power Supply
GND Processor Digital Circuit Ground
52 45 VCC2 +5V RTC Supply. VCC2 is isolated from VCC to isolate the RTC from digital noise.
GND2 RTC Circuit Ground
1， 25 18， 46 Reset Input. This pin contains a Schmitt voltage input to recognize external active
high reset inputs. The pin also employs an internal pulldown resistor to allow for a
29 22 combination of wired OR external reset sources. An RC is not required for power-up，
as the device provides this function internally.
26 19 Crystal Oscillator Pins. XTAL1 and_XTAL2 provide support for parallel-resonant，
AT-cut crystals. XTAL1 acts also as an input if there is an external clock source in
12 5 RST place of a crystal. XTAL2 is the output of the crystal amplifier.
23 16 XTAL2
24 17 XTAL1
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN NAME FUNCTION
PLCC TQFP
38 31 PSEN Program Store-Enable Output. This active-low signal is a chip enable for optional
ALE external ROM memory. PSEN provides an active-low pulse and_is driven high when
39 32 P0.0 (AD0) external ROM is not being accessed.
Address Latch-Enable Output. This pin latches the external address LSB from the
multiplexed address/data bus on Port 0. This signal is commonly connected to the
latch enable of an external 373 family transparent latch. ALE has a pulse width of
1.5 XTAL1 cycles and_a period of four XTAL1 cycles. ALE is forced high when the
device is in a Reset condition. ALE can be disabled and_forced high by writing
ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
50 43
49 42 P0.1 (AD1) Port 0 (AD0?AD7)， I/O. Port 0 is an open-drain， 8-bit， bidirectional I/O port. As an
48 41 P0.2 (AD2) alternate function Port 0 can function as the multiplexed address/data bus to access
off-chip memory. During the time when ALE is high， the LSB of a memory address
47 40 P0.3 (AD3) is presented. When ALE falls to a logic 0， the port transitions to a bidirectional data
46 39 P0.4 (AD4) bus. This bus is used to read external ROM and_read/ write external RAM memory
or peripherals. When used as a memory bus， the port provides active high drivers.
45 38 P0.5 (AD5) The reset condition of Port 0 is tri-state. Pullup resistors are required when using
44 37 P0.6 (AD6) Port 0 as an I/O port.
43 36 P0.7 (AD7)
3 48 P1.0 Port 1， I/O. Port 1 functions as both an 8-bit， bidirectional I/O port and_an alternate
functional interface for Timer 2 I/O， new External Interrupts， and_new Serial Port 1.
4 49 P1.1 The reset condition of Port 1 is with all bits at a logic 1. In this state， a weak pullup
holds the port high. This condition also serves as an input mode， since any external
circuit that writes to the port will overcome the weak pullup. When software writes a
5 50 P1.2 0 to any port pin， the device will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will
6 51 P1.3 cause a strong transition driver to turn on， followed by a weaker sustaining pullup.
Once the momentary strong driver turns off， the port again becomes the output high
(and_input) state. The alternate modes of Port 1 are outlined as follows.
7 52 P1.4
Port Alternate Function
P1.0 T2 External I/O for Timer/Counter 2
8 1 P1.5 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1 Serial Port 1 Input
P1.3 TXD1 Serial Port 1 Output
External Interrupt 2 (Positive Edge Detect)
9 2 P1.6 P1.4 INT2 External Interrupt 3 (Negative Edge Detect)
P1.5 INT3
P1.6 INT4 External Interrupt 4 (Positive Edge Detect)
External Interrupt 5 (Negative Edge Detect)
10 3 P1.7 P1.7 INT5
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN NAME FUNCTION
PLCC TQFP
30 23 P2.0 (AD8) Port 2 (A8?A15)， I/O. Port 2 is a bidirectional I/O port. The reset condition of
31 24 P2.1 (AD9) Port 2 is logic high. In this state， a weak pullup holds the port high. This condition
also serves as an input mode， since any external circuit that writes to the port will
32 25 P2.2 (AD10) overcome the weak pullup. When software writes a 0 to any port pin， the device
33 26 P2.3 (AD11) will activate a strong pulldown that remains on until either a 1 is written or a reset
occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver
34 27 P2.4 (AD12) to turn on， followed by a weaker sustaining pullup. Once the momentary strong
35 28 P2.5 (AD13) driver turns off， the port again becomes both the output high and_input state. As an
alternate function Port 2 can function as MSB of the external address bus. This
36 29 P2.6 (AD14) bus can be used to read external ROM and_read/write external RAM memory or
37 30 P2.7 (AD15) peripherals.
15 8 P3.0 Port 3， I/O. Port 3 functions as both an 8-bit， bi-directional I/O port and_an
alternate functional interface for external interrupts， Serial Port 0， Timer 0 and_1
Inputs， and_RD and_WR strobes. The reset condition of Port 3 is with all bits at a
16 9 P3.1 logic 1. In this state， a weak pullup holds the port high. This condition also serves
as an input mode， since any external circuit that writes to the port will overcome
17 10 P3.2 the weak pullup. When software writes a 0 to any port pin， the device will activate
a strong pulldown that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition driver to turn
18 11 P3.3 on， followed by a weaker sustaining pullup. Once the momentary strong driver
turns off， the port again becomes both the output high and_input state. The
alternate modes of Port 3 are outlined below.
19 12 P3.4 Port Alternate Function
P3.0 RXD0 Serial Port 0 Input
20 13 P3.5 P3.1 TXD0 Serial Port 0 Output
P3.2 INT0 External Interrupt 0
External Interrupt 1
P3.3 INT1
21 14 P3.6 P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input
External Data Memory Write Strobe
22 15 P3.7 P3.6 WR External Data Memory Read Strobe
P3.7 RD
42 35 EA External Access Input， Active Low. Connect to ground to use an external ROM.
VBAT Internal RAM is still accessible as determined by register settings. Connect to VCC
51 44 RTCX2 to use internal ROM.
RTCX1
27 20 N.C. VBAT Input. Connect to the power source that maintains SRAM and_RTC when
VCC < VBAT. Can be connected to a 3V lithium battery or a super cap. Connect to
28 21 GND if battery will not be used with device.
2， 11， 13， 4， 6， 7， Timekeeping Crystals. A 32.768kHz crystal between these pins supplies the time
14， 40， 33， 34， base for the RTC. The devices support both 6pF and_12.5pF load capacitance
41 crystals as selected by an SFR bit (described later). To prevent noise from
47 affecting the RTC， the RTCX2 and_RTCX1 pins should be guard-ringed with
GND2.
Not Connected. These pins should not be connected. They are reserved for use
with future devices in the family.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
COMPATIBILITY
The DS87C530/DS83C530 are fully static， CMOS 8051-compatible microcontrollers designed for high
performance. While remaining familiar to 8051 users， the devices have many new features. In general，
software written for existing 8051-based systems works without modification on the
DS87C530/DS83C530. The exception is critical timing since the high-speed microcontrollers perform its
instructions much faster than the original for any given crystal selection. The DS87C530/DS83C530 run
the standard 8051 instruction set. They are not pin compatible with other 8051s due to the timekeeping
crystal.
The DS87C530/DS83C530 provide three 16-bit timer/counters， full-duplex serial port (2)， 256 bytes of
direct RAM plus 1kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051
product. Timers will default to a 12 clock-per-cycle operation to keep their timing compatible with
original 8051 systems. However， timers are individually programmable to run at the new 4 clocks per
cycle if desired. The PCA is not supported.
The DS87C530/DS83C530 provide several new hardware features implemented by new Special Function
Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C530/DS83C530 feature a high-speed， 8051-compatible core. Higher speed comes not just
from increasing the clock frequency， but also from a newer， more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS87C530/DS83C530， the same machine cycle takes 4 clocks. Thus the fastest instruction， one machine
cycle， executes three times faster for the same crystal frequency. Note that these are identical instructions.
The majority of instructions on the DS87C530/DS83C530 will see the full 3-to-1 speed improvement.
Some instructions will get between 1.5 and_2.4 to 1 improvement. All instructions are faster than the
original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However， the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements
produce a peak instruction cycle in 121ns (8.25 MIPs). The Dual Data Pointer feature also allows the user
to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051 counterparts. Their effect on bits， flags， and_
other status functions is identical. However， the timing of each instruction is different. This applies both
in absolute and_relative number of clocks.
For absolute timing of real-time events， the timing of software loops can be calculated using a table in the
High-Speed Microcontroller Users Guide. However， counter/timers default to run at the older 12 clocks
per increment. In this way， timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
The relative time of two instructions might be different in the new architecture than it was previously. For
example， in the original architecture， the MOVX A， @DPTR instruction and_the MOV direct， direct
instruction used two machine cycles or 24 oscillator cycles. Therefore， they required the same amount of
time. In the DS87C530/DS83C530， the MOVX instruction takes as little as two machine cycles or eight
oscillator cycles but the MOV direct， direct uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterparts， they now have different execution times. This is because
the DS87C530/DS83C530 usually use one instruction cycle for each instruction byte. The user concerned
with precise program timing should examine the timing of each instruction for familiarity with the
changes. Note that a machine cycle now requires just 4 clocks， and_provides one ALE pulse per cycle.
Many instructions require only one cycle， but some require five. In the original architecture， all were one
or two cycles except for MUL and_DIV. Refer to the High-Speed Microcontroller Users Guide for
details and_individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS87C530/DS83C530. This
allows the device to incorporate new features but remain instruction-set compatible with the 8051.
EQUATE statements can be used to define the new SFR to an assembler or compiler. All SFRs contained
in the standard 80C52 are duplicated in this device. Table 1 shows the register addresses and_bit locations.
The High-Speed Microcontroller Users Guide describes all SFRs.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Table 1. Special Function Register Locations
*_Functions not present in the 80C52 are in bold.
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
P0.2 P0.1 P0.0 80h
P0 P0.7 P0.6 P0.5 P0.4 P0.3 81h
0 0 SEL 82h
SP GF0 STOP IDLE 83h
IT1 IT0 84h
DPL C/ T IE0 M0 85h
M1 86h
DPH MD2 MD0 87h
P1.2 MD1 P1.0 88h
DPL1 RGMD P1.1 BGS 89h
TRM1 RGSL TRM0 8Ah
DPH1 RB8_0 TRM0 RI_0 8Bh
P2.2 TI_0 P2.0 8Ch
DPS 0 0 0 0 0 EX1 P2.1 EX0 8Dh
ET0 8Eh
PCON SMOD_0 SMOD0 -- -- GF1 P3.2 P3.0 90h
PX1 P3.1 PX0 91h
TCON TF1 TR1 TF0 TR0 IE1 PT0 96h
RB8_1 RI_1 98h
TMOD GATE C/ T M1 M0 GATE RMS2 TI_1 RMS0 99h
RMS1 DME0 A0h
TL0 ALEOFF DME1 SPRA0 A8h
SPTA0 A9h
TL1 SPRA1 CP/ RL2 AAh
TR2 C/ T2 B0h
TH0 -- T2OE DCEN B8h
B9h
TH1 BAh
C0h
CKCON WD1 WD0 T2M T1M T0M C1h
C2h
P1 P1.7 P1.6 P1.5 P1.4 P1.3 C4h
C5h
EXIF IE5 IE4 IE3 IE2 XT/RG C7h
C8h
TRIM E4K X12/ 6 TRM2 TRM2 TRM1 C9h
CAh
SCON0 SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 CBh
SBUF0
P2 P2.7 P2.6 P2.5 P2.4 P2.3
IE EA ES1 ET2 ES0 ET1
SADDR0
SADDR1
P3 P3.7 P3.6 P3.5 P3.4 P3.3
IP -- PS1 PT2 PS0 PT1
SADEN0
SADEN1
SCON1 SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1
SBUF1
ROMSIZE -- -- -- -- --
PMR CD1 CD0 SWB -- XTOFF
STATUS PIP HIP LIP XTUP SPTA1
TA
T2CON TF2 EXF2 RCLK TCLK EXEN2
T2MOD -- -- -- -- --
RCAP2L
RCAP2H
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Table 1. Special Function Register Locations (continued)
*_Functions not present in the 80C52 are in bold.
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
FL P CCh
TL2 CDh
EWT RWT D0h
TH2 EX3 EX2 D8h
E0h
PSW CY AC F0 RS1 RS0 OV PX3 PX2 E8h
RTCIF RTCE F0h
WDCON SMOD_1 POR EPFI PFI WDIF WTRF F2h
F3h
ACC F4h
F5h
EIE -- -- ERTCI EWDI EX5 EX4 F8h
F9h
B FAh
FBh
RTASS FCh
FDh
RTAS 0 0 FEh
FFh
RTAM 0 0
RTAH 0 0 0
EIP -- -- PRTCI PWDI PX5 PX4
RTCC SSCE SCE MCE HCE RTCRE RTCWE
RTCSS
RTCS 0 0
RTCM 0 0
RTCH
RTCD0
RTCD1
NONVOLATILE FUNCTIONS
The DS87C530/DS83C530 provide two functions that are permanently powered if a user supplies an
external energy source. These are an on-chip RTC and_a nonvolatile SRAM. The chip contains all related
functions and_controls. The user must supply a backup source and_a 32.768kHz timekeeping crystal.
REAL-TIME CLOCK
The on-chip RTC keeps time of day and_calendar functions. Its time base is a 32.768kHz crystal between
pins RTCX1 and_RTCX2. The RTC maintains time to 1/256 of a second. It also allows a user to read (and_
write) seconds， minutes， hours， day of the week， and_date. Figure 2 shows the clock organization.
Timekeeping registers allow easy access to commonly needed time values. For example， software can
simply check the elapsed number of minutes by reading one register. Alternately， it can read the complete
time of day， including subseconds， in only four registers. The calendar stores its data in binary form.
While this requires software translation， it allows complete flexibility as to the exact value. A user can
start the calendar with a variety of selections since it is simply a 16-bit binary number of days. This
number allows a total range of 179 years beginning from 0000.
The RTC features a programmable alarm condition. A user selects the alarm time. When the RTC reaches
the selected value， it sets a flag. This will cause an interrupt if enabled， even in Stop mode. The alarm
consists of a comparator that matches the user value against the RTC actual value. A user can select_a
match for 1 or more of the sub-seconds， seconds， minutes， or hours. This allows an interrupt
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
automatically to occur once per second， once per minute， once per hour， or once per day. Enabling
interrupts with no match will generate an interrupt 256 times per second.
Software enables the timekeeper oscillator using the RTC enable bit in the RTC Control register (F9h).
This starts the clock. It can disable the oscillator to preserve the life of the backup energy-source if
unneeded. Values in the RTC Control register are maintained by the backup source through power failure.
Once enabled， the RTC maintains time for the life of the backup source even when VCC is removed.
The RTC will maintain an accuracy of 2 minutes per month at 25C. Under no circumstances are
negative voltages， of any amplitude， allowed on any pin while the device is in data retention mode
(VCC < VBAT). Negative voltages will shorten battery life， possibly corrupting the contents of internal
SRAM and_the RTC.
Figure 2. Real-Time Clock
NONVOLATILE RAM
The 1k x 8 on-chip SRAM can be nonvolatile if an external backup energy source is used. This allows the
device to log data or to store configuration settings. Internal switching circuits will detect the loss of VCC
and_switch SRAM power to the backup source on the VBAT pin. The 256 bytes of direct RAM are not
affected by this circuit and_are volatile.
CRYSTAL AND BACKUP SOURCES
To use the unique functions of the DS87C530/DS83C530， a 32.768kHz timekeeping crystal and_a backup
energy source are needed. The following describes guidelines for choosing these devices.
Timekeeping Crystal
The DS87C530/DS83C530 can use a standard 32.768kHz crystal as the RTC time base. There are two
versions of standard crystals available， with 6pF and_12.5pF load capacitance. The tradeoff is that the 6pF
uses less power， giving longer life while VCC is off， but is more sensitive to noise and_board layout. The
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
12.5pF crystal uses more power， giving a shorter battery backed life， but produces a more robust
oscillator. Bit 6 in the RTC Trim register (TRIM;_96h) must be programmed to specify the crystal type
for the oscillator. When TRIM.6 = 1， the circuit expects a 12.5pF crystal. When TRIM.6 = 0， it expects a
6pF crystal. This bit will be nonvolatile so these choices will remain while the backup source is present.
A guard ring (connected to the RTC ground) should encircle the RTCX1 and_RTCX2 pins.
Backup Energy Source
The DS87C530/DS83C530 use an external energy source to maintain timekeeping and_SRAM data
without VCC. This source can be either a battery or 0.47F super cap and_should be connected to the VBAT
pin. The nominal battery voltage is 3V. The VBAT pin will not source current. Therefore， a super cap
requires an external resistor and_diode to supply charge.
The backup lifetime is a function of the battery capacity and_the data retention current drain. This drain is
specified in the electrical specifications. The circuit loads the VBAT only when VCC has fallen below VBAT.
Thus the actual lifetime depends not only on the current and_battery capacity， but also on the portion of
time without power. A very small lithium cell provides a lifetime of more than 10 years.
Figure 3. Internal Backup Circuit
IMPORTANT APPLICATION NOTE
The pins on the DS87C530/DS83C530 are generally as resilient as other CMOS circuits. They have no
unusual susceptibility to electrostatic discharge (ESD) or other electrical transients. However， no pin on
the DS87C530/DS83C530 should ever be taken to a voltage below ground. Negative voltages on any
pin can turn on internal parasitic diodes that draw current directly from the battery. If a device pin is
connected to the outside world where it may be handled or come in contact with electrical noise，
protection should be added to prevent the device pin from going below -0.3V. Some power supplies can
give a small undershoot on power-up， which should be prevented. Application Note 93: Design
Guidelines for Microcontrollers Incorporating NV RAM discusses how to protect the
DS87C530/DS83C530 against these conditions.
MEMORY RESOURCES
Like the 8051， the DS87C530/DS83C530 use three memory areas. The total memory configuration of the
device is 16kB of ROM， 1kB of data SRAM and_256 bytes of scratchpad or direct RAM. The 1kB of data
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
space SRAM is read/write accessible and_is memory mapped. This on-chip SRAM is reached by the
MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes of register
mapped RAM and_is identical to the RAM found on the 80C52. There is no conflict or overlap among the
256 bytes and_the 1kB as they use different addressing modes and_separate instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed LCC should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise， the device may not meet the AC and_DC
parameters listed in the data sheet.
PROGRAM MEMORY ACCESS
On-chip ROM begins at address 0000h and_is contiguous through 3FFFh (16kB). Exceeding the
maximum address of on-chip ROM will cause the DS87C530/DS83C530 to access off-chip memory.
However， the maximum on-chip decoded address is selectable by software using the ROMSIZE feature.
Software can cause the microcontroller to behave like a device with less on-chip memory. This is
beneficial when overlapping external memory， such as Flash， is used.
The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the
memory map to access off-chip memory， then restored to access on-chip memory. In fact， all the on-chip
memory can be removed from the memory map allowing the full 64kB memory space to be addressed
from off-chip memory. ROM addresses that are larger than the selected maximum are automatically
fetched from outside the part via Ports 0 and_2. Figure 4 shows a depiction of the ROM memory map.
The ROMSIZE register is used to select_the maximum on-chip decoded address for ROM. Bits RMS2，
RMS1， RMS0 have the following effect:
RMS2 RMS1 RMS0 MAXIMUM ON-CHIP ROM ADDRESS
0 0 0 0kB
0 0 1 1kB
0 1 0 2kB
0 1 1 4kB
1 0 0 8kB
1 0 1
1 1 0 16kB (default)
1 1 1 Invalid--reserved
Invalid--reserved
The reset default condition is a maximum on-chip ROM address of 16kB. Thus no action is required if
this feature is not used. When accessing external program memory， the first 16kB would be inaccessible.
To select_a smaller effective ROM size， software must alter bits RMS2?RMS0. Altering these bits
requires a timed-access procedure.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For
example， assume that a device is executing instructions from internal program memory near the 12kB
boundary (~3000h) and_that the ROMSIZE register is currently configured for a 16kB internal program
space. If software reconfigures the ROMSIZE register to 4kB (0000h?0FFFh) in the current state， the
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
device will immediately jump to external program execution because program code from 4kB to 16kB
(1000h?3FFFh) is no longer located on-chip. This could result in code misalignment and_execution of an
invalid instruction. The recommended method is to modify the ROMSIZE register from a location in
memory that will be internal (or external) both before and_after the operation. In the above example， the
instruction which modifies the ROMSIZE register should be located below the 4kB (1000h) boundary， so
that it will be unaffected by the memory modification. The same precaution should be applied if the
internal program memory size is modified while executing from external program memory.
Off-chip memory is accessed using the multiplexed address/data bus on P0 and_the MSB address on P2.
While serving as a memory bus， these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA
overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or output enable
when Ports 0 and_2 fetch from external ROM.
Figure 4. ROM Memory Map
DATA MEMORY ACCESS
Unlike many 8051 derivatives， the DS87C530/DS83C530 contain on-chip data memory. The devices also
contain the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The
MOVX instruction accesses the on-chip data memory. Although physically on-chip， software treats this
area as though it was located off-chip. The 1kB of SRAM is between address 0000h and_03FFh.
Access to the on-chip data RAM is optional under software control. When enabled by software， the data
SRAM is between 0000h and_03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 03FFh automatically go to external memory through
Ports 0 and_2.
When disabled， the 1kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and_FFFFh goes to the expanded bus on Ports 0 and_2. This also is the default
condition. This default allows the DS87C530/DS83C530 to drop_into an existing system that uses these
addresses for other hardware and_still have full compatibility.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
The on-chip data area is software selectable using 2 bits in the Power Management Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent to
reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and_DME0 (PMR.0).
They have the following operation:
Table 2. Data Memory Access Control
DME1 DME0 DATA MEMORY ADDRESS MEMORY FUNCTION
External Data Memory (default condition)
0 0 0000h?FFFFh Internal SRAM Data Memory
External Data Memory
0 1 0000h?03FFh Reserved
0400h?FFFFh Internal SRAM Data Memory
Reserved--no external access
1 0 Reserved Read access to the status of lock bits
Reserved--no external access
0000h?03FFh
1 1 0400h?FFFBh
FFFCh
FFFDh?FFFh
Notes on the status byte read at FFFCh with DME1， 0 = 1， 1: Bits 2-0 reflect the programmed status of
the security lock bits LB2?LB0. They are individually set to a logic 1 to correspond to a security lock bit
that has been programmed. These status bits allow software to verify that the part has been locked before
running if desired. The bits are read-only.
Note: After internal MOVX SRAM has been initialized， changing bits DEM0/1 has no effect on the
contents of the SRAM.
STRETCH MEMORY CYCLE
The DS87C530/DS83C530 allow software to adjust the speed of off-chip data memory access. The
microcontrollers can perform the MOVX in as few as two instruction cycles. The on-chip SRAM uses
this speed and_any MOVX instruction directed internally uses two cycles. However， the time can be
stretched for interface to external devices. This allows access to both fast memory and_slow memory or
peripherals with no glue logic. Even in high-speed systems， it may not be necessary or desirable to
perform off-chip data memory access at full speed. In addition， there are a variety of memory-mapped
peripherals such as LCDs or UARTs that are slow.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
It allows the user to select_a Stretch value between 0 and_7. A Stretch of 0 will result in a two-machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset， the Stretch value will default to a 1， resulting in a three-cycle MOVX for any external access.
Therefore， off-chip RAM access is not at full speed. This is a convenience to existing designs that may
not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch
setting. When desiring maximum speed， software should select_a Stretch value of 0. When using very
slow RAM or peripherals， select_a larger Stretch value. Note that this affects data memory only and_the
only way to slow program memory (ROM) access is to use a slower crystal.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Using a Stretch value between 1 and_7 causes the microcontroller to stretch the read/write strobe and_all
related timing. Also， setup and_hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and_relaxed interface timing， allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications section. Table 3 shows the resulting strobe widths for each Stretch value. The memory
Stretch uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is
selected using bits CKCON.2?0. In the table， these bits are referred to as M2 through M0. The first
Stretch (default) allows the use of common 120ns RAMs without dramatically lengthening the memory
access.
Table 3. Data Memory Cycle Stretch Values
CKCON.2?0 MEMORY CYCLES RD OR WR STROBE STROBE WIDTH TIME
M2 M1 M0 WIDTH IN CLOCKS AT 33MHz
(ns)
0 0 0 2 (forced internal) 2 60
3 (default external) 4 121
0 0 1 8 242
4 12 364
0 1 0 5 16 485
6 20 606
0 1 1 7 24 727
8 28 848
1 0 0 9
1 0 1
1 1 0
1 1 1
DUAL DATA POINTER
The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C530/DS83C530， the standard data pointer is called DPTR， located at SFR addresses 82h and_83h.
These are the standard locations. Using DPTR requires no modification of standard code. The new DPTR
at SFR 84h and_85h is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer. Its location
is the lsb of the SFR location 86h. No other bits in register 86h have any effect and_are 0. The user
switches between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the
fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any
activity. Therefore it takes only one instruction to switch from a source to a destination address. Using the
Dual Data Pointer saves code from needing to save source and_destination addresses when doing a block
move. The software simply switches between DPTR and_1 once software loads them. The relevant
register locations are as follows.
DPL 82h Low byte original DPTR
High byte original DPTR
DPH 83h Low byte new DPTR
High byte new DPTR
DPL1 84h DPTR Select (lsb)
DPH1 85h
DPS 86h
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POWER MANAGEMENT
Along with the standard Idle and_power-down (Stop) modes of the standard 80C52， the
DS87C530/DS83C530 provide a new Power Management Mode. This mode allows the processor to
continue functioning， yet to save power compared with full operation. The DS87C530/DS83C530 also
feature several enhancements to Stop mode that make it more useful.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. During default operation， the DS87C530/DS83C530
use four clocks per machine cycle. Thus the instruction cycle rate is (Clock/4). At 33MHz crystal speed，
the instruction cycle speed is 8.25MHz (33/4). In PMM， the microcontroller continues to operate but uses
an internally divided version of the clock source. This creates a lower power state without external
components. It offers a choice of two reduced instruction cycle speeds (and_two clock sources - discussed
below). The speeds are (Clock/64) and_(Clock/1024).
Software is the only mechanism to invoke the PMM. Table 4 illustrates the instruction cycle rate in PMM
for several common crystal frequencies. Since power consumption is a direct function of operating speed，
PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of processing.
PMM 2 runs very slowly and_provides the lowest power consumption without stopping the CPU. This is
illustrated in Table 5.
Note that PMM provides a lower power condition than Idle mode. This is because in Idle， all clocked
functions such as timers run at a rate of crystal divided by 4. Since wake-up from PMM is as fast as or
faster than from Idle and_PMM allows the CPU to operate (even if doing NOPs)， there is little reason to
use Idle mode in new designs.
Table 4. Machine Cycle Rate
CRYSTAL SPEED FULL OPERATION PMM1 PMM2
(MHz) (4 CLOCKS) (64 CLOCKS) (1024 CLOCKS)
(MHz)
(kHz) (kHz)
11.0592 2.765
172.8 10.8
16 4.00
250.0 15.6
25 6.25
390.6 24.4
33 8.25
515.6 32.2
Table 5. Typical Operating Current in PMM
CRYSTAL SPEED FULL OPERATION PMM1 PMM2
(MHz) (4 CLOCKS) (64 CLOCKS) (1024 CLOCKS)
(mA)
(mA) (mA)
11.0592 13.1 5.3 4.8
16 17.2 6.4 5.6
25 25.7 8.1 7.0
33 32.8 9.8 8.2
