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The AHA4540 device is a single-chip Turbo Product Code (TPC) Forward Error Correction (FEC) Encoder/Decoder capable of 155 Mbit/sec (OC-3) data rates (up to 200 Mbit/sec channel rates). This device integrates both a TPC encoder and decoder, and can be operated in a full duplex mode. In addition to TPC coding, support is included for helical interleaving, synchronization mark insertion and detection, CRC computation, scrambling, and higher order modulation symbol mapping. Figure 1 shows the functional block diagram. The channel interface supports direct connection to various modulators and demodulators. Support for an arbitrary constellation mapping is included with external logic. The encode path accepts byte-wide data, computes and inserts a CRC, and scrambles the data before TPC encoding. After the error correction code (ECC) bits are inserted by the encoder, the data is helically interleaved, and block synchronization marks are inserted to assist the decoder. Finally, the data is mapped according to the constellation and output from the device. The decoder accepts input symbols via the demodulated in-phase (I) and quadrature (Q) components or alternately as soft metric inputs from an external demodulator. An internal block synchronizer searches for synchronization marks, rotating the input symbol phase as necessary. After synchronization is achieved, the data is helically deinterleaved and decoded by the TPC decoder. The output of the decoder is descrambled, and the CRC is computed to verify data integrity. Decoded data is output in a parallel, byte-wide fashion. Internal circuitry enables the transfer rate across all ports, generating a constant, non-burst data flow. In addition, control of an external VCO can be used to generate data clocks, greatly simplifying system clocking issues.
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