Key Features
VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9 and 10
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0°C to 95°C)
7.8 μs at 0°C to 85°C
3.9 μs at 85°C to 95°C
Commercial Temperature( 0°C to 95°C)
Industrial Temperature(-40°C to 95°C)
JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
Technical Attributes
Description Value Find similar Parts
Type DDR3 SDRAM
Maximum Random Access Time 20 ns
Number of Bits per Word 8 Bit
Operating Supply Voltage 1.5 V
Maximum Clock Rate 933 MHz
Organization 512M x 8
Data Bus Width 8 Bit
Mounting Surface Mount
Address Bus Width 16 Bit
Maximum Operating Current 42 mA
Number of I/O Lines 8 Bit
Package Dimensions 7.5 x 11 x 0.76 mm
Density 4 Gb
Operating Temperature 0 to 95 °C
Screening Level Commercial
Number of Banks 8
