3.3V CMOS 8-BIT REGISTER WITH CLOCK ENABLE AND 5 VOLT TOLERANT I/O

文件：68.03 Kbytes 页数：6 Pages

IDT

3.3V CMOS 8-BIT REGISTER WITH CLOCK ENABLE AND 5 VOLT TOLERANT I/O

文件：68.03 Kbytes 页数：6 Pages

IDT

3.3V CMOS 8-BIT REGISTER WITH CLOCK ENABLE AND 5 VOLT TOLERANT I/O

文件：68.03 Kbytes 页数：6 Pages

IDT

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

文件：95.56 Kbytes 页数：10 Pages

PHI

PHI

Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-

文件：236.19 Kbytes 页数：12 Pages

NEXPERIA

安世

Octal D-type flip-flop with data enable; positive-edge trigger

DESCRIPTION The 74LVC377 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • Wide supply voltage range of 1.2V to 3.6V • Conforms to JEDEC standard 8-1A • Inputs accept voltages up to 5.5V • CMOS low power consumption • Direct interface w

文件：95.56 Kbytes 页数：10 Pages

PHI

PHI